1. Field of the Invention
The present invention relates to an array substrate, and more particularly, to a method of fabricating an array substrate which includes a thin film transistor with an oxide semiconductor layer.
2. Discussion of the Related Art
With rapid development of information technologies, display devices for displaying a large amount of information have been promptly developed. More particularly, flat panel display (FPD) devices having a thin profile, light weight and low power consumption such as organic electroluminescent display (OLED) devices and liquid crystal display (LCD) devices have been actively pursued and are replacing the cathode ray tubes (CRTs).
Among the liquid crystal display devices, active matrix type liquid crystal display devices, which include thin film transistors to control on/off the respective pixels, have been widely used because of their high resolution, color rendering capability and superiority in displaying moving images.
In addition, organic electroluminescent display devices have been recently spotlighted because they have many merits as follows: the organic electroluminescent display devices have high brightness and low driving voltages; because they are self-luminous, the organic electroluminescent display devices have excellent contrast ratios and ultra thin thicknesses; the organic electroluminescent display devices have a response time of several micro seconds, and there are advantages in displaying moving images; the organic electroluminescent display devices have wide viewing angles and are stable under low temperatures; since the organic electroluminescent display devices are driven by a low voltage of direct current (DC) 5V to 15V, it is easy to design and manufacture driving circuits; and the manufacturing processes of the organic electroluminescent display device are simple since only deposition and encapsulation steps are required. In the organic electroluminescent display devices, active matrix type display devices also have been widely used because of their low power consumption, high definition and large-sized possibility.
Each of the active matrix type liquid crystal display devices and the active matrix type organic electroluminescent display devices includes an array substrate having thin film transistors as switching elements to control on/off their respective pixels.
FIG. 1 is a cross-sectional view of illustrating an array substrate for a liquid crystal display device according to the related art. FIG. 1 shows a cross-section of a pixel region including a thin film transistor in the array substrate.
In FIG. 1, a gate line (not shown) and a data line (not shown) are formed on a substrate 11 and cross each other to define a pixel region P. A gate electrode 15 is formed at a switching region TrA of the pixel region P.
A gate insulating layer 18 is formed on the gate electrode 15, and a semiconductor layer 28, which includes an active layer 22 of intrinsic amorphous silicon and ohmic contact layers 26 of impurity-doped amorphous silicon, is formed on the gate insulating layer 18.
Source and drain electrodes 36 and 38 are formed on the ohmic contact layers 26. The source and drain electrodes 36 and 38 correspond to the gate electrode 15 and are spaced apart from each other. The gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38 sequentially formed at the switching region TrA constitute a thin film transistor Tr.
A passivation layer 42 is formed on the source and drain electrodes 36 and 38 and the exposed active layer 22 all over the substrate 11. The passivation layer 42 has a drain contact hole 45 exposing a portion of the drain electrode 38. A pixel electrode 50 is formed independently in each pixel region P on the passivation layer 42. The pixel electrode 50 contacts the drain electrode 38 through the drain contact hole 45.
Here, although not shown in the figure, a semiconductor pattern is formed under the data line. The semiconductor pattern has a double-layered structure including a first pattern of the same material as the ohmic contact layers 26 and a second pattern of the same material as the active layer 22.
In the semiconductor layer 28 formed at the switching region TrA of the related art array substrate, the active layer 22 of intrinsic amorphous silicon has different thicknesses depending on the position. That is, a portion of the active layer 22 exposed by selectively removing the ohmic contact layers 26 has a first thickness t1 and a portion of the active layer 22 under the ohmic contact layers 26 has a second thickness t2, which is thicker than the first thickness t1. The different thicknesses of the different portions of the active layer 22 result from a manufacturing method, and this decreases the output characteristics of the thin film transistor Tr and negatively affects the performance of the thin film transistor Tr because the active layer 22 between the source and drain electrodes 36 and 38, which becomes a channel of the thin film transistor Tr, has a reduced thickness.
To address this problem, a thin film transistor having an oxide semiconductor layer of a single layer, which does not need the related art ohmic contact layers and which uses an oxide semiconductor material as an active layer, has been introduced.
FIG. 2 is a cross-sectional view of illustrating a pixel region for an array substrate that includes a thin film transistor having such an oxide semiconductor layer according to the related art.
In FIG. 2, an oxide semiconductor layer 63 is formed at each pixel region P on a transparent insulating substrate 61. A gate electrode 69 is formed in correspondence to a central portion of the oxide semiconductor layer 63, and a gate insulating layer 66 is disposed between the oxide semiconductor layer 63 and the gate electrode 69.
At this time, the oxide semiconductor layer 63 includes an active area 63a and source and drain areas 63b. The active area 63a corresponds to the gate electrode 69 and has a semiconducting property. The source and drain areas 63b are exposed at both sides of the gate insulating layer 66 and have conductive properties different from the active area 63a. 
An inter insulating layer 72 of an inorganic insulating material is formed on the gate electrode 69 and the gate insulating layer 66. The inter insulating layer 72 includes first and second semiconductor contact holes 74a and 74b, which expose the source and drain areas 63b of the oxide semiconductor layer 63, respectively, at both sides of the gate electrode 69.
Source and drain electrodes 76 and 77 are formed on the inter insulating layer 72. The source and drain electrodes 76 and 77 contact the source and drain areas 63b through the first and second semiconductor contact holes 74a and 74b, respectively.
A passivation layer 78 is formed on the source and drain electrodes 76 and 77, and a pixel electrode 85 is formed on the passivation layer in the pixel region P. The pixel electrode 85 contacts the drain electrode 77 through a drain contact hole 80 of the passivation layer 78.
In the array substrate including the thin film transistor OTr of FIG. 2 having the oxide semiconductor layer 63, the oxide semiconductor layer 63 has a single-layered structure without the ohmic contact layers. Thus, the oxide semiconductor layer 63 is not exposed to etching gases used in a dry-etching process for forming the ohmic contact layers 26 of FIG. 1. Therefore, the output characteristics of the thin film transistor OTr are prevented from being lowered and minimized.
However, in the array substrate including the thin film transistor OTr of FIG. 2 having the oxide semiconductor layer 63, to transmit a signal voltage applied from the source electrode 76 to the drain electrode 77 through the oxide semiconductor layer 63, it is needed to decrease the contact resistance between the oxide semiconductor layer 63 and the source and drain electrodes 76 and 77. Therefore, to increase conductive properties of portions of the oxide semiconductor layer 63 contacting the source and drain electrodes 76 and 77, hydrogen plasma treatment may be performed to the oxide semiconductor layer 63 exposed outside the gate insulating layer 66, as shown in FIG. 3, which is a cross-sectional view of illustrating an array substrate including a thin film transistor having an oxide semiconductor layer in a step of performing hydrogen plasma treatment.
However, even though the source and drain areas 63b of the oxide semiconductor layer 63 is treated by hydrogen plasma, the source and drain areas 63b of the oxide semiconductor layer 63 contacting the source and drain electrodes 76 and 77 gradually lose the conductive properties as time passes, and the characteristics of the oxide thin film transistor are lowered.